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Cypress Semiconductor /psoc63 /FLASHC /FM_CTL /TEST_CTL

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Interpret as TEST_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TEST_MODE0 (PN_CTL)PN_CTL 0 (TM_PE)TM_PE 0 (TM_DISPOS)TM_DISPOS 0 (TM_DISNEG)TM_DISNEG 0 (EN_CLK_MON)EN_CLK_MON 0 (CSL_DEBUG)CSL_DEBUG 0 (ENABLE_OSC)ENABLE_OSC 0 (UNSCRAMBLE_WA)UNSCRAMBLE_WA

Description

Test mode control

Fields

TEST_MODE

Test mode control: ‘0’-‘31’: TBD
PN_CTL

Postive/negative margin mode control: ‘0’: negative margin control ‘1’: positive margin control
TM_PE

PUMP_EN override: Pump Enable =PUMP_EN | PE_TM
TM_DISPOS

Test mode positive pump disable
TM_DISNEG

Test mode negative pump disable
EN_CLK_MON

1: enables the oscillator output monitor
CSL_DEBUG

Engineering Debug Register
ENABLE_OSC

0’: the oscillator enable logic has control over the internal oscillator ‘1’: forces oscillator enable HI
UNSCRAMBLE_WA

See BSN-242 memo ‘0’: normal ‘1’: disables the Word Address scrambling

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data